This invention relates to semiconductor integrated circuits and, more particularly, to a signal detection circuit. The function of the signal detection circuit is to compare an amplitude of a differential input signal to a comparator threshold voltage and to produce an output signal which is either high or low depending on whether the signal's amplitude is less than or greater than the comparator threshold voltage. This invention is similar to a method of detecting an amplitude of a signal which uses a current-source-biased comparator, but replaces the current source with a short to a power supply terminal and adds input signal level-shifters, providing for a much-improved differential input signal common-mode range.
FIG. 1 is a schematic diagram illustrating a signal detection circuit of the prior art. A differential input signal comprises input signals INP and INM, with INP coupled to the gate terminal of M8, and INM coupled to the gate terminal of M9. A compare voltage THRESH, coupled to a gate terminal of M4, is set to a voltage equal to an average of INP and INM plus the comparator threshold voltage. The drain terminals of M8 and M9 are coupled together and to output terminal OUT1, and the source terminals of M4, M8, and M9 are coupled together and to current source I1. A current mirror comprising M6 and M7 has an input coupled to the drain of M4 and an output coupled to OUT1. N-type transistors M4, M8, and M9 are of equal size, and p-type transistors M6 and M7 are of equal size. When the amplitude of the differential input signal exceeds the comparator threshold voltage, input signal INP or INM is more positive than THRESH, and output terminal OUT1 will then be substantially low, indicating detection of the differential input signal. When the amplitude of the differential input signal is less than the comparator threshold voltage, input signal INP or INM is always more negative than THRESH, and output terminal OUT1 will then be substantially high. For most practical values of the compare voltage THRESH, during a transition of the differential input signal from one state to another (for example, from a “one” state to a “zero” state), OUT1 may tend to momentarily pulse from a low to a high voltage and then return to a low voltage when the transition is complete. In one embodiment, this pulse is inhibited with a capacitor coupled to OUT1.